High cost of design reviews versus high risk of inadequate design review.
A design reviewer can spend more time doing a thorough design review than the designer took to design corresponding parts of the circuit. This is because the designer is usually well down the learning curve for the circuit topology, parts, and packaging of the design, which may be unfamiliar to the reviewer. This can make design review unaffordable or impractical and can result in the following problems.
No design review is performed.
The design review is a formality only. Often this is in the form of a check list that is checked satisfactory with little or no real review. The design agency can state that a design review has been performed, but the review is meaningless.
Yet effective design review should be considered mandatory, since all designers have blind spots and it is risky to release a design that has not been reviewed by another knowledgeable designer.
Applies to all designs although the application here is for switching-mode power supplies and power electronics circuits in general.
Solutions range from elimination of the design review to full blown design reviews costing more than corresponding elements of the original design. A compromise, the topological design review, is a cost effective solution.
Most topologies, parts, and packaging techniques have known problem areas that have been discussed in the literature. Pareto's law implies reviewing the top 20% of these problems areas should catch 80% of the problems. A considerable savings. This is the approach taken in topological design review.
A topological design review. The salient features of a topological design review are:
- A topological design-review uses prior knowledge of the common pitfalls associated with specific topologies, components, packaging methods, environments, and applications.
- The reviewer then concentrates on these pitfall areas using simple models to decide if there is a likely problem.
- The output of the review is a list of potential problems flagged for further analysis or test.
- The reviewer is usually an experienced designer in the design field trained in the technique.
The topological design review was developed between 1972 and 1980 by Jerrold Foutz while head of the Power Electronics Branch at the Naval Ocean Systems Center, San Diego, California (NOSC).
At the time, power supplies caused over 50% of field failures for many Navy equipments. Effective design reviews appeared to be a necessity. Yet, a thorough design-review of a switching-mode power supply using conventional approaches could approach the cost of corresponding elements of the original circuit design.
Most Navy Program Managers could not afford this level-of-effort, even if trained reviewers were available --- which they were not.
Program managers needed an affordable design-review method. The solution was to concentrate on what was known about the primary problems associated with specific circuit topologies and components.
Although there are thousands of switching-mode power supply designs, they can be categorized into several basic topologies. Designers have analyzed these topologies, identified their peculiar pitfalls, and published the results in the technical literature.
By identifying the topology to which any individual design belongs, the reviewer can concentrate on whether the designer has addressed the particular pitfalls of that topology.
For example, if a two-state boost-derived topology is used, then the most important questions for that design relate to stability, transient response, and audio-susceptibility, because of the difficulty in compensation for the right-half-plane zero present in these topologies.
Several analytical tools were collected or developed to aid in a quick evaluation of various topologies.
The first tool was to characterize various topologies and control techniques in the state-plane. Duke University was the leader in this powerful and under-utilized approach. The paper by Burns and Wilson is an example. Some papers out of Virginia Polytechnic Institute & State University (VPI) also use the technique. The author expanded this approach in unpublished work and used it in the initial topological design reviews.
However, the canonical models (Middlebrook and Cuk) and design oriented analysis developed by Dr. Middlebrook at the California Institute of Technology became the primary tools of the topological design review.
Where tools were missing, the Navy sponsored work to refine the tools used, for example Middlebrook's work on input filter interactions and Cuk's work on reducing electromagnetic interference (EMI) in switching-mode power supplies leading to the Cuk Converter.
In practice, an annotated schematic and parts information are the key to the topological design review.
The schematic should be annotated with input/output voltages, reference diode voltages, inductance values, transformer turns ratio and primary inductance, frequency of switching waveforms, and any other information needed for numerical calculations or part identification. The topology is then identified, the shortcomings of that topology determined, and simple models are used to make numerical and impedance-paper calculations to determine possible problem areas.
Besides the pitfalls that are peculiar to an individual topology, there are pitfalls that are common to all topologies. Also, different component types, packaging methods, etc., have their associated pitfalls. The topological design-review considers these.
The reviewer considers current-ripple stress in filter capacitors and staying within transistor safe-operating-area curves because these are common and serious problems that are often overlooked. The reviewer ignores other stresses, since the effort is redundant to the normally required MIL-HDBK-217 or in-house reliability analysis.
The major shortcomings of the topological design review are flagging non-problems as problems (because of the simple models used), and not catching all design problems.
Flagging non-problems as problems is a minor shortcoming in practice, since the next step is to examine in more detail problem areas flagged by the topological design-review. Where no problem exists, test or further analysis quickly resolves this.
The possibility of not catching all problems is true of other design-review methods because of the finite time and resources available.
The major benefits of the topological design review are:
When a program can afford a more thorough design review, the topological design-review locates problems early. This reduces the cost of subsequent computer aided analysis and exhaustive testing because it gives direction to the analysis and testing. It weeds out most of the problems and avoids several iterations of expensive test and analysis procedures.
Using the tools developed for the topological design review, useful results can be obtained in less than a four hour level-of-effort. The topological design review reaches the point of diminishing returns after a 160 hour level-of-effort. At this point, conventional design-review techniques start to be equally cost effective.
Many programs cannot afford an exhaustive design review that would catch all problems. For these programs, the more affordable topological design-review is an attractive alternative to no design review or a review that only goes through the motions. It will catch the most probable problems and may catch all problems.
The method proved highly successful on dozens of programs. For example, on one program it resulted in documented cost savings of over $200,000 with 40 hours of review effort. These reviews kept power supply development from being the critical-path development item on several programs.
At various stages of its development, the Navy explained the technique to many of their contractors. Often the presenter reviewed a contractor's power supply in real time to show the technique.
Contractors briefed in this manner included IBM, Hughes, Raytheon, McDonnell Douglas, General Dynamics, General Electric, GTE, Honeywell, Control Data Corporation, Texas Instruments, and Rockwell International.
The algorithm for the topological design review is:
- Gather materials
- Description of application
- Requirement documents
- Test specifications
- Schematics - if missing, add zener voltages, transformer turns ratio and primary inductance, and inductor inductance.
- Parts list - identify commercial type, not just in-house numbers.
- Part description. For magnetics include core, coil, and test data, for filters include the schematic with parasitics and any other available information.
- Review the application and the requirement documents and make a list of required functions and limits. Flag any missing requirements.
- Look at the schematic (redraw if necessary) and partition circuit into functions.
- Compare requirements to circuit function. Flag any discrepancies.
- Determine approach taken for each function and the pitfalls associated with that approach.
- Use simple models to look at each pitfall and to determine if circuit meets requirements. Flag any discrepancies.
- Repeat appropriate steps for components and packaging.
- Summarize the problems and possible solutions. Recommend further analysis and tests.
- Recommend actions to take (change requirement or circuit) if problems are real.
After funding Middlebrook's work on input filter interaction with switching-mode power supplies, I carefully read the resulting paper. It took me 40 hours, including reading all the references and making sure I understood what I was reading. My conclusion was that very few engineers would understand this at the working level having only the paper to read.
Therefore I asked Dr. Middlebrook if he could put together a one week seminar that would take an engineer from the bachelor-degree level to the level where he/she could understand and employ the techniques used in the paper. He thought he could since he had been teaching similar design-oriented analysis techniques in his famous analog circuit design course at Caltech. Dr. Middlebrook still teaches design-oriented analysis in a commercial seminar.
I invited the top power supply and analog designers from Navy laboratories to attend the seminar at no cost except travel and per diem costs. There were 20 attendees, the seminar limit, from virtually all the Navy labs across the country.
The reaction I remember the best is the anger of the top analog designer at NOSC. He wanted to know why didn't they teach these techniques in university circuit design classes? For twenty years he had been doing it the hard way and he resented all the time he had wasted before he learned these techniques.
I immediately started using the techniques in topological design reviews. I could tell designers more about their circuits in twenty minutes than what they knew about them after months of analysis and lab work. Now the techniques are well known, but then it seemed like black magic to them.
I could tell dozens of anecdotes, but will limit it to one.
A Navy program manager had asked to me review the designs of five design agencies before down selecting from five vendors to three vendors. At one vendor, after giving my management and engineering briefings (the origin of this hypertext) we gathered around the table to discuss the actual design which was due to be delivered to the Navy the next week.
Within 20 minutes the review found that there was a window in the input to output transfer function that actually amplified the noise and that there was no chance the design would pass MIL-STD-461 CS01 tests. It took another hour to convince the design engineers, using conventional techniques, that this was the case. The chief engineer was called in and then other company management. In spite of the inputs of the Navy engineers and their own engineers, management insisted that they had used the basic design for years and there was no problem with the design. (The problem could have been fixed in less than a day with changes of some resistor and capacitor values that did not affect the printed wiring boards or mechanical design.)
My advice to the Navy program office was to setup for MIL-STD-461 CS01 tests and to run the test as soon as the hardware was received. It was run the day the power supply was received and failed just as predicted.
The vendor was dropped in the cut the same week. Not because of the design, which with a simple fix would have been one of the better designs. They were cut because of the attitude of the company management. They didn't listen when both the Navy and their own engineers told them they were wrong. Engineering projects are difficult enough without having to work with difficult management.
On the Web
Here are some websites related to design review.